IEEE

Design of high-precision FFT based on VHDL and analysis of code coverage

Abstract: This paper uses structured design to implement the floating-FFT by VHDL with ISE5.3 and simulates it by ModelSim. The data pathways in this project are in the form of 32-bit single precision ...
IEEE

ModelSim/Simulink co-simulation of sensorless PMSM speed control system with EKF estimator and adaptive fuzzy controller

Abstract: Based on the extended Kalman filter (EKF) estimator and adaptive fuzzy controller (AFC), the design of a sensorless speed control IP (Intellectual Property) for PMSM (Permanent Magnet ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
GitHub

Working with FPGA and VHDL

This repository contains my hands-on work and practical sessions (TPs) with FPGA and VHDL. As part of my learning process, I am documenting each practical session, using the ALTERA Cyclone V DE-1 SoC ...
electronicsforu

JOB: Validation Engineer II At Microchip Technology In Hyderabad

This position is an excellent opportunity for someone willing to work on the latest technologies and play a critical role in providing a roadmap for IP and IP solutions. This is a hands-on technical ...
GitHub

Interfacing VHDL and foreign languages with VUnit

Three main approaches are used to co-simulate (co-execute) VHDL sources along with software applications written in a different language (typically C/C++): Verilog Procedural Interface (VPI), also ...