Design-Reuse

Building an FPGA FIFO without using logic recourses

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...
Electronic Design

FIFO Family Specializes In Solving Network Queuing And Scheduling Problems

Based on a new architecture that combines high-speed queuing logic with an embedded FIFO memory core, the 72V51xxx family of multi-queue first-in-first-out (FIFO) ICs is designed to solve queuing and ...
EDN

IDT integrates multi-queuing logic and FIFO memory for fast networks

SANTA CLARA, Calif.–Integrated Device Technology Inc. here has integrated high-speed queuing logic and first-in, first-out memory to offer a new series of multi-queue FIFOs for fast networking ...
EDN

RTL coding architecture affects power estimation & analysis

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...
Design-Reuse

Making SPI-4.2 Implementations More Efficient: Part 1

The SPI-4.2 interface has quickly achieved the industry-wide recognition and is highly accepted as standard high-speed interface in the networking chip space. However, creating an efficient SPI-4.2 ...